The 65xx family of microprocessors, consisting of the MOS Technology 6502 and its derivatives, the WDC 65C02, WDC 65C802 and WDC 65C816, and CSG 65CE02, all handle interrupts in a similar fashion. There are three hardware interrupt signals common to all 65xx processors and one software interrupt, the instruction. The WDC 65C816 adds a fourth hardware interrupt—, useful for implementing virtual memory architectures—and the software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor of some type (e.g., a floating point processor).
Interrupt types
The hardware interrupt signals are all active low, and are as follows: RESETa reset signal, level-triggered NMIa non-maskable interrupt, edge-triggered IRQa maskable interrupt, level-triggered ABORTa special-purpose, non-maskable interrupt (65C816 only, see below), level-triggered
The detection of a signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt request disable flag in the status register and loads the program counter with the values stored at the processor initialization vector (–) before commencing execution. If operating in native mode, the 65C816/65C802 are switched back to emulation mode and stay there until returned to native mode under software control.
The detection of an or signal, as well as the execution of a instruction, will cause the same overall sequence of events, which are, in order: The processor completes the current instruction and updates registers or memory as required before responding to the interrupt. 65C816/65C802 when operating in native mode: The program bank register (, the part of the address bus) is pushed onto the hardware stack. The most significant byte (MSB) of the program counter () is pushed onto the stack. The least significant byte (LSB) of the program counter is pushed onto the stack. The status register () is pushed onto the stack. The interrupt disable flag is set in the status register. 65C816/65C802: is loaded with . is loaded from the relevant vector (see tables).
The behavior of the 65C816 when is asserted differs in some respects from the above description and is separately discussed below.
Note that the processor does not push the accumulator and index registers on to the stack—code in the interrupt handler must perform that task, as well as restore the registers at the termination of interrupt processing, as necessary. Also note that the vector for is the same as that for in all eight bit 65xx processors, as well as in the 65C802/65C816 when operating in emulation mode. When operating in native mode, the 65C802/65C816 provide separate vectors for and .
When set, the interrupt request disable flag (the bit in the status register) will disable detection of the signal, but will have no effect on any other interrupts (however, see below section on the instruction implemented in WDC CMOS processors). Additionally, with the 65(c)02 or the 65C816/65C802 operating in emulation mode, the copy of the status register that is pushed on to the stack will have the flag set if a (software interrupt) was the cause of the interrupt, or cleared if an was the cause. Hence the interrupt service routine must retrieve a copy of the saved status register from where it was pushed onto the stack and check the status of the flag in order to distinguish between an and a . This requirement is eliminated when operating the 65C802/65C816 in native mode, due to the separate vectors for the two interrupt types.
interrupt
The 65C816's interrupt input is intended to provide the means to redirect program execution when a hardware exception is detected, such as a page fault or a memory access violation. Hence the processor's response when the input is asserted (negated) is different from when and/or are asserted. Also, achieving correct operation in response to requires that the interrupt occur at the proper time during the machine cycle, whereas no such requirement exists for or .