The Vortex86 is a computing system-on-a-chip (SoC) based on a core compatible with the x86 microprocessor family. It is produced by DM&P Electronics, but originated with Rise Technology.
History
Vortex86 previously belonged to SiS, which got the basic design from Rise Technology. SiS sold it to DM&P Electronics in Taiwan.
Before adopting the Vortex86 series, DM&P manufactured the M6117D, an Intel 386SX compatible, 25–40 MHz SoC.
CPU
Vortex86 CPUs implement the IA-32 architecture but which instructions are implemented varies depending on the model. Vortex86SX and the early versions of Vortex86 do not have a floating point unit (FPU). Any code that runs on i586 but does not use floating point instructions will run on these models. Any i586 code will run on Vortex86DX and later. Some Linux kernels (by build-time option) emulate the FPU on any CPU that is missing one, so a program that uses i586-level floating point instructions will work on any Vortex86 family CPU under such a kernel, albeit more slowly on a model with no FPU. The more advanced models have FPUs that have i686-level instructions, such as FUCOMI.
Code intended for i686 may fail on some models because they lack a Conditional Move (CMOV) instruction. Compilers asked to optimize code for a more advanced CPU (for example the GNU Compiler with its -march=i686 option) generate code that uses CMOV. Linux systems intended to run on i686 are generally not compatible with these Vortex86 models because the GNU C Library, when built for i686, uses a CMOV instruction in its assembly language strcmp function, which its dynamic loader (ld.so) uses. Hence, no program that uses shared libraries can execute.
Below are the properties of a Vortex86 original CPU reported by the Linux kernel tool /proc/cpuinfo.
Note that this CPU is a later version with an FPU. processor : 0 vendor_id : SiS SiS SiS cpu family : 5 model : 0 model name : 05/00 stepping : 5 cpu MHz : 199.978 fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu tsc cx8 mmx up bogomips : 399.95 clflush size : 32 cache_alignment : 32 address sizes : 32 bits physical, 32 bits virtual power management:
Software Compatibility
DM&P maintained an embedded Linux distribution customized to use the SoCs features. Other operating systems may work depending on the SoC model, including various RTOS systems such as QNX and VxWorks, Linux distributions, FreeBSD or various versions of Microsoft Windows systems such as Windows Embedded Compact or Windows IoT.
The ability to identify Vortex86 processors was added to Linux 5.16, released in January 2022.
Versions
Vortex86 original
The Vortex86 (M6127D) is a rebadged SiS 551 system-on-chip (SoC). The CPU core is derived from the Rise mP6, which has three integer and MMX pipelines and branch prediction.
Vortex86SX
Introduced in February 2007, the Vortex86SX is an x86-compatible System-on-chip (SoC) with built-in north and south bridge on a 0.13 micron process in a 27x27 mm 581-ball BGA package.
The CPU core is typically clocked at 300 MHz and is compatible with the 486SX instruction set. It has a six-stage pipeline with a direct-mapped write-through 16 KB Data + 16 KB Instruction L1 cache but, unlike the Vortex86, lacks L2 cache and an FPU. The memory controller allows 16-bit wide access to SDRAM up to 128 MB at 133 MHz and DDR2 up to 256 MB at 166 MHz.
The SoC includes
PCI 2.1 interface at 33 MHz
ISA bus interface
ATA controller with 2 channels at Ultra-DMA 100
Fast Ethernet MAC
USB 2.0 host with 4 ports
5 FIFO UART ports compatible with 16C550/16C552 at up to 460.8 kbps
GPIO with 40 pins
Embedded 256 KB flash memory
Unlike the original Vortex86, it does not integrate video or audio controllers.
Vortex86DX
Introduced in August 2008, the Vortex86DX retains the same BGA package as the SX and is pin-compatible. It is built on a 90 nm process.
The CPU core is clocked at 600 MHz to 1 GHz (2.02 W @ 800 MHz ) and improves on the SX with a 4-way 16 KB Data + 16 KB Instruction L1 cache, adds a 4-way 256 KB L2 cache, in write-through or write-back mode, and an FPU. The memory controller drops the ability to use SDRAM but increases the amount and speed of DDR2 memory it can drive to 1GB and 333 MHz.
The SoC adds the ability to function as a USB 1.1 client on 1 port and increases the embedded flash capacity to 2 MB.