In electronics, emitter-coupled logic (ECL) is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven bipolar junction transistor (BJT) differential amplifier with single-ended input and limited emitter current to avoid the saturated (fully on) region of operation and its slow turn-off behavior. As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic (CSL), current-mode logic (CML) or current-switch emitter-follower (CSEF) logic.
In ECL, the transistors are never in saturation, the input and output voltages have a small swing (0.8 V), the input impedance is high and the output impedance is low. As a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. In addition, the essentially constant current draw of the differential amplifiers minimises delays and glitches due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.
ECL's major disadvantage is that each gate continuously draws current, which means that it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent.
The equivalent of emitter-coupled logic made from FETs is called source-coupled logic (SCFL).
A variation of ECL in which all signal paths and gate inputs are differential is known as differential current switch (DCS) logic.
History
ECL was invented in August 1956 at IBM by Hannon S. Yourke. Originally called current-steering logic, it was used in the Stretch, IBM 7090, and IBM 7094 computers. The logic was also called a current-mode circuit. It was also used to make the ASLT circuits in the IBM 360/91.
Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level." In Yourke's design, the two logic reference levels differed by 3 volts. Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."
Instead of alternating NPN and PNP stages, another coupling method employed Zener diodes and resistors to shift the output logic levels to be the same as the input logic levels.
Beginning in the early 1960s, ECL circuits were implemented on monolithic integrated circuits and consisted of a differential-amplifier input stage to perform logic and followed by an emitter-follower stage to drive outputs and shift the output voltages so they will be compatible with the inputs. The emitter-follower output stages could also be used to perform wired-or logic.
Motorola introduced their first digital monolithic integrated circuit line, MECL I, in 1962. Motorola developed several improved series, with MECL II in 1966, MECL III in 1968 with 1-nanosecond gate propagation time and 300 MHz flip-flop toggle rates, and the 10,000 series (with lower power consumption and controlled edge speeds) in 1971. The MECL 10H family was introduced in 1981. Fairchild introduced the F100K family.
The ECLinPS ("ECL in picoseconds") family was introduced in 1987. ECLinPS has 500 ps single-gate delay and 1.1 GHz flip-flop toggle frequency. The ECLinPS family parts are available from multiple sources, including Arizona Microtek, Micrel, National Semiconductor, and ON Semiconductor.
The high power consumption of ECL meant that it has been used mainly when high speed is a vital requirement. Older high-end mainframe computers, such as the Enterprise System/9000 members of IBM's ESA/390 computer family, used ECL, as did the Cray-1; and first-generation Amdahl mainframes. (Current IBM mainframes use CMOS.) Beginning in 1975, Digital Equipment Corporation's highest performance processors were all based on multi-chip ECL CPUs—from the ECL KL10 through the ECL VAX 8000 and finally the VAX 9000. By 1991, the CMOS NVAX was launched which offered comparable performance to the VAX 9000 despite costing 25 times less and consuming considerably less power. The MIPS R6000 computers also used ECL. Some of these computer designs used ECL gate arrays.