Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.
Intel instructions
i386 instructions
The following instructions were introduced in the Intel 80386, but later discontinued:
Itanium instructions
These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation.
MPX instructions
These instructions were introduced in 6th generation Intel Core "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs.
Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds.
Hardware Lock Elision
The Hardware Lock Elision feature of Intel TSX is marked in the Intel SDM as removed from 2019 onwards. This feature took the form of two instruction prefixes, XACQUIRE and XRELEASE, that could be attached to memory atomics/stores to elide the memory locking that they represent.
VP2Intersect instructions
The VP2INTERSECT instructions (an AVX-512 subset) were introduced in Tiger Lake (11th generation mobile Core processors), but were never officially supported on any other processor, and are now considered deprecated.
Instructions specific to Xeon Phi processors
"Knights Corner" instructions
The first generation Xeon Phi processors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is available − the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for the KMOV, KNOT and KORTEST instructions − these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names).
Most of these KNC-unique instructions are similar but not identical to instructions in AVX-512 − later Xeon Phi processors replaced these instructions with AVX-512.
Early versions of AVX-512 avoided the instruction encodings used by KNC's MVEX prefix, however with the introduction of Intel APX (Advanced Performance Extensions) in 2023, some of the old KNC MVEX instruction encodings have been reused for new APX encodings. For example, both KNC and APX accept the instruction encoding as valid, but assign different meanings to it: KNC: APX:
"Knights Landing" and "Knights Mill" instructions
Some of the AVX-512 instructions in the Xeon Phi "Knights Landing" and later models belong to the AVX-512 subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors. The ER and PF subsets were introduced in "Knights Landing" − the 4FMAPS and 4VNNIW instructions were later added in "Knights Mill".
The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where: EVEX.W is used to specify floating-point format (0=FP32, 1=FP64) The bottom opcode bit is used to select between packed and scalar operation (0: packed, 1:scalar) For a given operation, all the scalar/packed variants belong to the same AVX-512 subset. The instructions all support result masking by opmask registers. The AVX512ER instructions also all support broadcast of memory operands. The only supported vector width is 512 bits.