Alder Lake is Intel's codename for the 12th generation of Intel Core processors based on a hybrid architecture utilizing Golden Cove performance cores and Gracemont efficient cores. It is fabricated using Intel's Intel 7 process, previously referred to as Intel 10 nm Enhanced SuperFin (10ESF). The 10ESF has a 10%-15% boost in performance over the 10SF used in the mobile Tiger Lake processors. Intel officially announced 12th Gen Intel Core CPUs on October 27, 2021. Intel officially announced 12th Gen Intel Core mobile CPUs and non-K series desktop CPUs on January 4, 2022. Intel officially announced the launch of Alder Lake-P and -U series on February 23, 2022, and Alder Lake-HX series on May 10, 2022.
History
Fabricated using Intel's Intel 7 process, which was previously referred to as Intel 10 nm Enhanced SuperFin (10ESF), Intel officially announced 12th Gen Intel Core CPUs on October 27, 2021. Intel then officially announced 12th Gen Intel Core mobile CPUs and non-K series desktop CPUs on January 4, 2022.
It further was announced in January 2022 that Intel Alder Lake would use a hybrid architecture combining performance and efficiency cores, similar to ARM big.LITTLE. This was the second Intel's hybrid architecture, after the mobile-only Lakefield released in June 2020. While the desktop Alder Lake processors were already on the market by January 2022, the mobile processors were not, although release was expected early that year. Starting cost were USD $289 for the Core i5-12600K. Gracemont was the name given to the efficiency cores, while Golden Cove cores were set for tasks such as gaming and video processing. First laptop tests were performed later that month, with PCMag positively reviewing the Core i9-12900HK, stating the H series represented "Intel's enthusiast line," with "the same hybrid designs" also in the P-series and U-series chips to come out later that year.
In April 2022, press reported on "hints" that Intel was working on Alder Lake-X. Intel officially announced the HX processor series on May 10, 2022, including Core i5, Core i7 and Core i9 models, when Intel announced "seven new mobile processors for the 12th Gen Intel Core mobile family at its Intel Vision event. With the lineup based on Intel's desktop Alder Lake chips, it was named the Alder Lake-HX series, or 12th-gen Core HX, with the Core i9-12950HX as the flagship and Intel's first 16-core chip designed for laptops.
Features
CPU
Golden Cove performance cores ("P-cores") Dedicated floating-point adders New 6-wide instruction decoder (from 4-wide in Rocket Lake/Tiger Lake) with the ability to fetch up to 32 bytes of instructions per cycle (from 16) 12 execution ports (from 10) 512 reorder-buffer entries (from 352) 6-wide μOP allocations (from 5) TAGE-like directional branch predictor (with a global history size of 194 taken branches) μOP cache size increased to 4K entries (up from 2.25K) AVX-VNNI, a VEX-coded variant of AVX512-VNNI for 256-bit vectors AVX-512 (including FP16) is present but disabled by default to match E-cores. On early revisions of microprocessors it still can be enabled on some motherboards with some BIOS versions by disabling the E-cores. Intel has physically fused off AVX-512 on later revisions of Alder Lake CPUs manufactured in early 2022 and onward. ~18% IPC uplift. Gracemont efficient cores ("E-cores") Aggregated into 4-core modules with a shared L2 cache 256 reorder-buffer entries (up from 208 in Tremont) 17 execution ports (up from 12) AVX2, FMA and AVX-VNNI Skylake-like IPC. New instruction set extensions: PTWRITE SERIALIZE HRESET User-mode wait (WAITPKG): TPAUSE, UMONITOR, UMWAIT Up to 1 TB/s interconnect between cores Intel Thread Director (only for CPUs with P and E cores), which is a marketing name for Enhanced Hardware Feedback Interface (EHFI). This is a hardware technology to assist the OS thread scheduler with more efficient load distribution between heterogeneous CPU cores. Enabling this new capability requires support in the operating system. Architectural last branch records (LBRs) Hypervisor-managed linear address translation (HLAT) Control-flow enforcement technology (CET), including support for indirect branch tracking (IBT) and shadow stack (SS) 4–30 MB L3 cache Cores: up to 8 P-cores and 8 E-cores on desktop up to 6 P-cores and 8 E-cores on mobile (UP3 designs) up to 2 P-cores and 8 E-cores on ultra mobile (UP4 designs) only P-cores feature hyper-threading