The Display Data Channel, or DDC, is a collection of protocols for digital communication between a computer display and a graphics adapter that enable the display to communicate its supported display modes to the adapter and that enable the computer host to adjust monitor parameters, such as brightness and contrast.
Like modern analog VGA connectors, the DVI and DisplayPort connectors include pins for DDC, but DisplayPort only supports DDC within its optional Dual-Mode DP (DP++) feature in DVI/HDMI mode.
The standard was created by the Video Electronics Standards Association (VESA).
Overview
The DDC suite of standards aims to provide Plug and Play and DPMS power management experiences for computer displays.
DDC1 and DDC2B/Ab/B+/Bi protocols are a physical link between a monitor and a video card, which was originally carried on either two or three pins in a 15-pin analog VGA connector.
Extended display identification data (EDID) is a companion standard; it defines a compact binary file format describing the monitor's capabilities and supported graphics modes, stored in a read-only memory (EEPROM) chip programmed by the manufacturer of the monitor. The format uses a description block containing 128 bytes of data, with optional extension blocks to provide additional information. The most current version is Enhanced EDID (E-EDID) Release A, v2.0.
The first version of the DDC standard was adopted in August 1994. It included the EDID 1.0 format and specified DDC1, DDC2B and DDC2Ab physical links.
DDC version 2, introduced in April 1996, split EDID into a separate standard and introduced the DDC2B+ protocol.
DDC version 3, December 1997, introduced the DDC2Bi protocol and support for VESA Plug and Display and Flat Panel Display Interface on separate device addresses, requiring them to comply with EDID 2.0.
The DDC standard has been superseded by E-DDC in 1999.
Physical link
Prior to the DDC, the VGA standard had reserved four pins in the analog VGA connector, known as ID0, ID1, ID2 and ID3 (pins 11, 12, 4 and 15) for identification of monitor type. These ID pins, attached to resistors to pull one or more of them to ground (GND), allowed for the definition of the monitor type, with all open (n/c, not connected) meaning "no monitor".
In the most commonly documented scheme, the ID3 pin was unused and only the 3 remaining pins were defined. The ID0 was pulled to GND by color monitors, while the monochrome monitors pulled ID1 to GND. Finally, the ID2 pulled to GND signaled a monitor capable of 1024×768 resolution, such as IBM 8514. In this scheme, the input states of the ID pins would encode the monitor type as follows:
More elaborate schemes also existed that used all of the 4 ID pins while manipulating the HSync and VSync signals in order to extract 16 bits (4 ID pin values for each of the 4 combinations of HSync and VSync states) of monitor identification.
DDC changed the purpose of the ID pins to incorporate a serial link interface. However, during the transition, the change was not backwards-compatible and video cards using the old scheme could have problems if a DDC-capable monitor was connected. The DDC signal can be sent to or from a video graphics array (VGA) monitor with the I2C protocol using the master's serial clock and serial data pins.
DDC1
DDC1 is a simple, low-speed, unidirectional serial link protocol. Pin 12, ID1 functions as a data line that continuously transmits the 128-byte EDID block, and the data clock is synchronised with vertical sync, providing typical clock rates of 60 to 100 Hz.
Very few display devices implemented this protocol.
DDC2
The most common version, called DDC2B, is based on I²C, a serial bus. Pin 12, ID1, of the VGA connector is used as the data pin of the I²C bus, and the formerly-unused pin 15 is the I²C clock. Pin 9, previously used as a mechanical key, supplies +5V DC power (up to 50mA) to power the EEPROM. With this, the host can read the EDID even if the monitor is powered off. Though I²C is fully bidirectional and supports multiple bus-masters, DDC2B is unidirectional and allows only one bus master -- the graphics adapter. The monitor acts as a slave device at the 7-bit I²C address 50h, and provides 128-256 bytes of read-only EDID. Because this access is always a read, the first I²C octet will always be A1h.