In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology.
Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a 7 nm process called N7 in June 2016, before Samsung began mass production of their 7 nm process called 7LPP devices in 2018. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips were manufactured by TSMC.
In 2019, AMD released their "Rome" (EPYC 2) processors for servers and datacenters, which are based on TSMC's N7node and feature up to 64 cores and 128 threads. They also released their "Matisse" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the GlobalFoundries' 14 nm (14HP) process, while the Matisse's I/O die uses the GlobalFoundries' 12 nm (12LP+) process. The Radeon RX 5000 series is also based on TSMC's N7 process.
Since at least 1997, however, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. However, the smallest dimension within an individual transistor, the fin width, can be 7 nm. TSMC and Samsung's 10 nm (10 LPE) processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density.
History
Technology demos
7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6 nm silicon-on-insulator (SOI) MOSFET. In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.
In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.
In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process, with a cell area of 0.027 square micrometers (550 F2) with reasonable risk production yields.
Expected commercialization and technologies
In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017. In April 2017, TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm (N7FF+) process, with extreme ultraviolet lithography (EUV). TSMC's 7 nm production plans, as of early 2017, were to use deep ultraviolet (DUV) immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm (N7FF+) production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.
In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.
In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm (Intel 4) manufacturing process. The company has not published any expected values for feature lengths at this process node.
In April 2018, TSMC announced volume production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.
In May 2018, Samsung announced production of 7 nm (7LPP) chips this year. ASML Holding NV is their main supplier of EUV lithography machines.
In August 2018, GlobalFoundries announced it was stopping development of 7 nm chips, citing cost.
On October 28, 2018, Samsung announced their second generation 7 nm process (7LPP) had entered risk production and should enter mass production in 2019.
On January 17, 2019, for the Q4 2018 earnings call, TSMC mentioned that different customers will have "different flavors" of second generation 7 nm.
On April 16, 2019, TSMC announced their 6 nm process called (CLN6FF, N6), which is expected to be in mass products from 2021. N6 uses EUVL in up to 5 layers, compared to up to 4 layers in their N7+ process.